Hulpprogramma's
Manual
MakeTestBench
VHDL File:
Package: use ieee.numeric_std.all;
Package: use std.textio.all;
Synchronous Description
Clock Pin:
Start:
low
high
Half Clock Period:
Reset Pin:
Active:
low
high
Active Period:
Stimuli
File
Text Field
Stimulus File:
Preamble:
Body:
Use the
Browse...
button to search the VHDL file.
Select options.
Click at
Generate
button.
